基本信息
源码名称:EDA电子密码锁Verilog语言
源码大小:0.22M
文件格式:.7z
开发语言:MATLAB
更新时间:2021-07-08
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   源码介绍

设计一个密码锁的控制电路,当输入正确代码时,输出开锁信号以推动执行机构工作,用红灯亮﹑绿灯熄灭表示关锁,用绿灯亮﹑红灯熄灭表示开锁;

在锁的控制电路中储存一个可以修改的4位代码,当开锁按钮开关(可设置成6 位至8位,其中实际有效为4位,其余为虚设)的输入代码等于储存代码时,开锁;

从第一个按钮触动后的5 秒内若未将锁打开,则电路自动复位并进入自锁状态,使之无法再打开,并发出报警信号。



顶层文件

module password_lock_top(

input clk,rst,setting,

input set_ok,

input [7:0] sw,

input [3:0] key,

output led,led_R,led_G

);

wire clk_200hz;

wire pulse;

wire [1:0] pw_in,led_state;

wire [3:0] key_debounce;

wire [7:0] new_password;

div_200hz u1(.clk(clk),

.clk_200hz(clk_200hz)); //分频

key_debounce u2(.clk(clk_200hz),

.key(key),

.key_debounce(key_debounce)); //按键消抖

key_pulse u3(.clk(clk),

.key(|key_debounce),

.pulse(pulse)); //按键产生脉冲

key_password u4(.key(key_debounce),

.password(pw_in)); //按键输入密码

password_compare u5(.clk_pulse(pulse),

.rst(rst),

.pw_in(pw_in),

.pw_sw(new_password),

.led_state(led_state)); //密码比较

lock_result u6(.clk(clk),

.led_state(led_state),

.led_R(led_R),

.led_G(led_G),

.led(led)); //密码处理

set_password u7(.key_clk(set_ok),

.rst(rst),

.set(setting),

.in(sw),

.out(new_password)); //设置密码

endmodule




按键防抖

module key_debounce(

input clk,

input [3:0] key,

output [3:0] key_debounce

);

reg [3:0] key_r,key_rr,key_rrr;

always @(posedge clk) begin

key_rrr = key_rr;

key_rr = key_r;

key_r = key;

end

assign key_debounce = key_rrr & key_rr & key_r;

endmodule




密码输入

module key_password(

input [3:0] key,

output reg [1:0] password

);

always @ (key)

case (key)

4'b0001: password =2'b00; //输入密码 0

4'b0010: password =2'b01; //输入密码 1

4'b0100: password =2'b10; //输入密码 2

4'b1000: password =2'b11; //输入密码 3

default: password =2'b00;

endcase

endmodule




密码比较

module password_compare(

input clk_pulse,rst,

input [1:0] pw_in,

input [7:0] pw_sw,

output [1:0] led_state

);

parameter led_on=2'b00,

led_off=2'b11,

led_blink=2'b10;

parameter s0=4'h0,

s1=4'h1,

s2=4'h2,

s3=4'h3,

s4=4'h4,

e1=4'h5,

e2=4'h6,

e3=4'h7,

e4=4'h8;

reg [3:0] next_st = s0;

always @ (posedge clk_pulse or posedge rst)

if (rst) next_st = s0;

else begin

case(next_st)

s0: begin

if(pw_sw[7:6]==pw_in) next_st =s1;

else next_st = e1;

end

s1: begin

if(pw_sw[5:4]==pw_in) next_st =s2;

else next_st = e2;

end

s2: begin

if(pw_sw[3:2]==pw_in) next_st =s3;

else next_st = e3;

end

s3: begin

if(pw_sw[1:0]==pw_in) next_st =s4;

else next_st = e4;

end

s4: next_st = s0;

e1: next_st = e2;

e2: next_st = e3;

e3: next_st = e4;

e4: next_st = s0;

default: next_st = s0;

endcase

end

assign led_state = (next_st == s4) ? led_on:(next_st ==e4)?

led_blink: led_off;

endmodule




结果锁定

module lock_result(

input clk,

input [1:0] led_state,

output reg led,led_R,led_G

);

reg [23:0] cnt;

parameter led_on =2'b00,led_off=2'b11,led_blink=2'b10;

always @(posedge clk) begin

cnt = cnt 1;

if(led_state == led_on ) begin led_R=1;led_G=0;led=0;end

else begin

if(led_state ==led_off )begin  led_R=0;led_G=1;led=0;end

else begin led=1;led_R=0;led_G=0; end

end

end

endmodule

//设置密码模块

module set_password(

input key_clk,rst,

input set,

input [7:0] in,

output reg [7:0] out

);

always @ ( key_clk or rst)

if (rst) out <= 8'b11100100; //初始密码 3210

else if(set) out <= in; //设置新密码

endmodule