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   源码介绍

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Contents
1 ARM 32-bit Cortex-M0  limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 STM32L031x4/6 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Additional current consumption in Standby mode . . . . . . . . . . . . . . . . . . 8
2.1.3 Unexpected system reset when waking up from Stop mode with
regulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Timer2 and Timer21 alternate functions not available on PA8, PB6
and PA11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5 SRAM size limited to 4 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.6 Flash memory wakeup issue when waking up from Stop or Sleep
with Flash in power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.7 Schmitt trigger hysteresis disabled on PH0 and PH1 inputs . . . . . . . . . . 9
2.1.8 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.9 I2C and USART cannot wake up the device from Stop mode . . . . . . . . 10
2.1.10 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . 10
2.1.11 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . 11
2.2 ADC limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1 Overrun flag might not be set when converted data have not been read
before new data are written . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Comparator limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit
in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Output of comparator 2 cannot be internally connected to input 1
of low-power timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 12
2.4.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 12
2.5 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Wrong behaviors in Stop mode when waking up from Stop mode is
disabled in I2C peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Wrong data sampling when data set-up time (tSU;DAT) is smaller than
 one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DocID027842 Rev 3 3/18
STM32L031x4/6 Contents
3
2.6.1 BSY bit may stay high at the end of a SPI data transfer in slave mode . 14
2.6.2 Last data bit or CRC calculation may be corrupted for the data received
in master mode depending on the feedback communication
clock timing with respect to the APB clock . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3 Limited SPI frequency when peripheral is configured in Master
reception or in Slave transmission mode and VDD is below 2.7 V . . . . 15
2.7 USART limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7.1 Start bit detected too soon when sampling for NACK signal
from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7.2 Break request can prevent the Transmission Complete flag (TC)
from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7.3 nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17