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源码名称：S32K14X系列MCU硬件手册.pdf(共2023页)
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更新时间：2020-05-23
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源码介绍
汽车电子级芯片，s32K系列单片机参考手册
Contents Section number Title Page Chapter 1 About This Manual 1.1 Audience....................................................................................................................................................................... 49 1.2 Organization..................................................................................................................................................................49 1.3 Module descriptions......................................................................................................................................................49 1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 50 1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 51 1.4 Register descriptions.....................................................................................................................................................52 1.5 Conventions.................................................................................................................................................................. 53 1.5.1 Notes, Cautions, and Warnings......................................................................................................................53 1.5.2 Numbering systems........................................................................................................................................53 1.5.3 Typographic notation..................................................................................................................................... 54 1.5.4 Special terms.................................................................................................................................................. 54 Chapter 2 Introduction 2.1 Overview.......................................................................................................................................................................57 2.2 S32K1xx Series introduction........................................................................................................................................ 57 2.2.1 S32K14x.........................................................................................................................................................57 2.2.2 S32K11x ........................................................................................................................................................59 2.3 Feature summary...........................................................................................................................................................60 2.4 Block diagram...............................................................................................................................................................63 2.5 Feature comparison.......................................................................................................................................................64 2.5.1 Differences between S32K14x and S32K11x................................................................................................66 2.6 Applications.................................................................................................................................................................. 67 2.7 Module functional categories........................................................................................................................................68 2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................69 2.7.2 Arm Cortex-M0 Core Modules....................................................................................................................70 2.7.3 System modules............................................................................................................................................. 70 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 3 Section number Title Page 2.7.4 Memories and memory interfaces..................................................................................................................71 2.7.5 Power Management........................................................................................................................................72 2.7.6 Clocking......................................................................................................................................................... 72 2.7.7 Analog modules............................................................................................................................................. 73 2.7.8 Timer modules............................................................................................................................................... 73 2.7.9 Communication interfaces............................................................................................................................. 74 2.7.10 Debug modules.............................................................................................................................................. 75 Chapter 3 Memory Map 3.1 Introduction...................................................................................................................................................................77 3.2 SRAM memory map.....................................................................................................................................................77 3.2.1 S32K14x: SRAM memory map ....................................................................................................................77 3.2.2 S32K11x: SRAM memory map ....................................................................................................................77 3.3 Flash memory map........................................................................................................................................................78 3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................78 3.4.1 Read-after-write sequence and required serialization of memory operations................................................79 3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................80 3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 81 Chapter 4 Signal Multiplexing and Pin Assignment 4.1 Introduction...................................................................................................................................................................83 4.2 Functional description...................................................................................................................................................83 4.3 Pad description..............................................................................................................................................................84 4.4 Default pad state........................................................................................................................................................... 85 4.5 Signal Multiplexing sheet............................................................................................................................................. 86 4.5.1 IO Signal Table ............................................................................................................................................. 86 4.5.2 Input muxing table......................................................................................................................................... 88 4.6 Pinout diagrams............................................................................................................................................................ 89 Chapter 5 Security Overview S32K1xx Series Reference Manual, Rev. 9, 09/2018 4 NXP Semiconductors Section number Title Page 5.1 Introduction...................................................................................................................................................................91 5.2 Device security..............................................................................................................................................................91 5.2.1 Flash memory security................................................................................................................................... 91 5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................92 5.2.3 Device Boot modes........................................................................................................................................ 93 5.3 Security use case examples...........................................................................................................................................93 5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 93 5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 94 5.3.3 Secure communication...................................................................................................................................95 5.3.4 Component protection....................................................................................................................................96 5.3.5 Message-authentication example................................................................................................................... 97 5.4 Steps required before failure analysis...........................................................................................................................98 5.5 Security programming flow example (Secure Boot).................................................................................................... 99 Chapter 6 Safety Overview 6.1 Introduction...................................................................................................................................................................101 6.2 S32K1xx safety concept............................................................................................................................................... 102 6.2.1 Cortex-M4/M0 Structural Core Self Test (SCST).......................................................................................103 6.2.2 ECC on RAM and flash memory...................................................................................................................104 6.2.3 Power supply monitoring............................................................................................................................... 104 6.2.4 Clock monitoring........................................................................................................................................... 105 6.2.5 Temporal protection.......................................................................................................................................105 6.2.6 Operational interference protection............................................................................................................... 105 6.2.7 CRC................................................................................................................................................................107 6.2.8 Diversity of system resources........................................................................................................................ 107 Chapter 7 CM4 Overview 7.1 Arm Cortex-M4F core configuration............................................................................................................................109 7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 110 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 5 Section number Title Page 7.1.2 System Tick Timer.........................................................................................................................................110 7.1.3 Debug facilities.............................................................................................................................................. 110 7.1.4 Caches............................................................................................................................................................ 111 7.1.5 Core privilege levels...................................................................................................................................... 111 7.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 112 7.2.1 Interrupt priority levels.................................................................................................................................. 112 7.2.2 Non-maskable interrupt..................................................................................................................................113 7.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 113 7.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................114 7.3.1 Wake-up sources............................................................................................................................................ 114 7.4 FPU configuration.........................................................................................................................................................115 7.5 JTAG controller configuration......................................................................................................................................116 Chapter 8 CM0 Overview 8.1 Arm Cortex-M0 core introduction..............................................................................................................................117 8.1.1 Buses, interconnects, and interfaces.............................................................................................................. 118 8.1.2 System tick timer........................................................................................................................................... 118 8.1.3 Debug facilities.............................................................................................................................................. 118 8.1.4 Core privilege levels...................................................................................................................................... 118 8.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................119 8.2.1 Interrupt priority levels.................................................................................................................................. 119 8.2.2 Non-maskable interrupt..................................................................................................................................119 8.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 119 8.3 AWIC introduction....................................................................................................................................................... 120 8.3.1 Wake-up sources............................................................................................................................................ 120 Chapter 9 Micro Trace Buffer (MTB) 9.1 Introduction...................................................................................................................................................................123 9.1.1 Overview........................................................................................................................................................123 S32K1xx Series Reference Manual, Rev. 9, 09/2018 6 NXP Semiconductors Section number Title Page 9.1.2 Features.......................................................................................................................................................... 125 9.1.3 Modes of operation........................................................................................................................................ 126 9.2 Memory map and register definition.............................................................................................................................126 9.2.1 MTB_DWT Memory Map.............................................................................................................................127 Chapter 10 Miscellaneous Control Module (MCM) 10.1 Chip-specific MCM information.................................................................................................................................. 137 10.2 Introduction...................................................................................................................................................................138 10.2.1 Features.......................................................................................................................................................... 138 10.3 Memory map/register descriptions............................................................................................................................... 138 10.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................139 10.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 140 10.3.3 Core Platform Control Register (MCM_CPCR)............................................................................................141 10.3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 144 10.3.5 Process ID Register (MCM_PID).................................................................................................................. 147 10.3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 148 10.3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................149 10.3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................152 10.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................156 10.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 157 10.3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................158 10.3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................................................................................... 159 10.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 160 10.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................160 10.4 Functional description...................................................................................................................................................161 10.4.1 Interrupts........................................................................................................................................................ 161 Chapter 11 System Integration Module (SIM) 11.1 Chip-specific SIM information.....................................................................................................................................163 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 7 Section number Title Page 11.1.1 SIM register bitfield implementation.............................................................................................................163 11.2 Introduction...................................................................................................................................................................163 11.2.1 Features.......................................................................................................................................................... 163 11.3 Memory map and register definition.............................................................................................................................164 11.3.1 SIM register descriptions............................................................................................................................... 164 Chapter 12 Port Control and Interrupts (PORT) 12.1 Chip-specific PORT information..................................................................................................................................191 12.1.1 Number of PCRs............................................................................................................................................ 191 12.1.2 Finding address for PORTx_PCRn ...............................................................................................................192 12.1.3 I/O configuration sequence ........................................................................................................................... 192 12.1.4 Digital input filter configuration sequence ................................................................................................... 193 12.2 Introduction...................................................................................................................................................................194 12.3 Overview.......................................................................................................................................................................194 12.3.1 Features.......................................................................................................................................................... 194 12.3.2 Modes of operation........................................................................................................................................ 195 12.4 External signal description............................................................................................................................................195 12.5 Detailed signal description............................................................................................................................................196 12.6 Memory map and register definition.............................................................................................................................196 12.6.1 Pin Control Register n (PORT_PCRn).......................................................................................................... 198 12.6.2 Global Pin Control Low Register (PORT_GPCLR)......................................................................................201 12.6.3 Global Pin Control High Register (PORT_GPCHR).....................................................................................201 12.6.4 Global Interrupt Control Low Register (PORT_GICLR).............................................................................. 202 12.6.5 Global Interrupt Control High Register (PORT_GICHR).............................................................................202 12.6.6 Interrupt Status Flag Register (PORT_ISFR)................................................................................................ 203 12.6.7 Digital Filter Enable Register (PORT_DFER).............................................................................................. 204 12.6.8 Digital Filter Clock Register (PORT_DFCR)................................................................................................204 12.6.9 Digital Filter Width Register (PORT_DFWR).............................................................................................. 205 12.7 Functional description...................................................................................................................................................205 S32K1xx Series Reference Manual, Rev. 9, 09/2018 8 NXP Semiconductors Section number Title Page 12.7.1 Pin control...................................................................................................................................................... 205 12.7.2 Global pin control.......................................................................................................................................... 206 12.7.3 Global interrupt control..................................................................................................................................207 12.7.4 External interrupts..........................................................................................................................................207 12.7.5 Digital filter....................................................................................................................................................208 Chapter 13 General-Purpose Input/Output (GPIO) 13.1 Chip-specific GPIO information...................................................................................................................................209 13.1.1 Instantiation information................................................................................................................................209 13.1.2 GPIO ports memory map............................................................................................................................... 209 13.1.3 GPIO register reset values .............................................................................................................................210 13.2 Introduction...................................................................................................................................................................210 13.2.1 Features.......................................................................................................................................................... 211 13.2.2 Modes of operation........................................................................................................................................ 211 13.2.3 GPIO signal descriptions............................................................................................................................... 211 13.3 Memory map and register definition.............................................................................................................................212 13.3.1 GPIO register descriptions............................................................................................................................. 212 13.4 Functional description...................................................................................................................................................220 13.4.1 General-purpose input....................................................................................................................................220 13.4.2 General-purpose output..................................................................................................................................220 Chapter 14 Crossbar Switch Lite (AXBS-Lite) 14.1 Chip-specific AXBS-Lite information..........................................................................................................................223 14.1.1 Crossbar Switch master assignments............................................................................................................. 223 14.1.2 Crossbar Switch slave assignments................................................................................................................223 14.2 Introduction...................................................................................................................................................................224 14.2.1 Features.......................................................................................................................................................... 224 14.3 Functional Description..................................................................................................................................................225 14.3.1 General operation...........................................................................................................................................225 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 9 Section number Title Page 14.3.2 Arbitration......................................................................................................................................................225 14.4 Initialization/application information........................................................................................................................... 227 Chapter 15 Memory Protection Unit (MPU) 15.1 Chip-specific MPU information................................................................................................................................... 229 15.1.1 MPU Slave Port Assignments........................................................................................................................229 15.1.2 MPU Logical Bus Master Assignments.........................................................................................................230 15.1.3 Current PID.................................................................................................................................................... 230 15.1.4 Region descriptors and slave port configuration............................................................................................230 15.2 Introduction...................................................................................................................................................................231 15.3 Overview.......................................................................................................................................................................231 15.3.1 Block diagram................................................................................................................................................ 231 15.3.2 Features.......................................................................................................................................................... 232 15.4 MPU register descriptions.............................................................................................................................................233 15.4.1 MPU Memory map........................................................................................................................................ 233 15.4.2 Control/Error Status Register (CESR)........................................................................................................... 236 15.4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 238 15.4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 239 15.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................241 15.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................242 15.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................243 15.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................246 15.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................247 15.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................248 15.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................251 15.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 253 15.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)............................................... 256 15.5 Functional description...................................................................................................................................................259 15.5.1 Access evaluation macro................................................................................................................................259 S32K1xx Series Reference Manual, Rev. 9, 09/2018 10 NXP Semiconductors Section number Title Page 15.5.2 Putting it all together and error terminations................................................................................................. 261 15.5.3 Power management........................................................................................................................................ 261 15.6 Initialization information.............................................................................................................................................. 262 15.7 Application information................................................................................................................................................262 Chapter 16 Peripheral Bridge (AIPS-Lite) 16.1 Chip-specific AIPS information................................................................................................................................... 265 16.1.1 Instantiation information................................................................................................................................265 16.1.2 Memory maps................................................................................................................................................ 265 16.2 Introduction...................................................................................................................................................................266 16.2.1 Features.......................................................................................................................................................... 267 16.2.2 General operation...........................................................................................................................................267 16.3 Memory map/register definition................................................................................................................................... 267 16.3.1 AIPS register descriptions..............................................................................................................................267 16.4 Functional description...................................................................................................................................................311 16.4.1 Access support............................................................................................................................................... 311 Chapter 17 Direct Memory Access Multiplexer (DMAMUX) 17.1 Chip-specific DMAMUX information......................................................................................................................... 313 17.1.1 Number of channels ...................................................................................................................................... 313 17.1.2 DMA transfers via TRGMUX trigger............................................................................................................313 17.2 Introduction...................................................................................................................................................................314 17.2.1 Overview........................................................................................................................................................314 17.2.2 Features.......................................................................................................................................................... 314 17.2.3 Modes of operation........................................................................................................................................ 315 17.3 Memory map/register definition................................................................................................................................... 315 17.3.1 DMAMUX register descriptions....................................................................................................................315 17.4 Functional description...................................................................................................................................................317 17.4.1 DMA channels with periodic triggering capability........................................................................................317 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 11 Section number Title Page 17.4.2 DMA channels with no triggering capability.................................................................................................320 17.4.3 Always-enabled DMA sources...................................................................................................................... 320 17.5 Initialization/application information........................................................................................................................... 321 17.5.1 Reset...............................................................................................................................................................321 17.5.2 Enabling and configuring sources..................................................................................................................321 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.1 Chip-specific eDMA information ................................................................................................................................325 18.1.1 Seamless eDMA transfer .............................................................................................................................. 325 18.1.2 Number of channels ...................................................................................................................................... 326 18.2 Introduction...................................................................................................................................................................326 18.2.1 eDMA system block diagram........................................................................................................................ 326 18.2.2 Block parts..................................................................................................................................................... 327 18.2.3 Features.......................................................................................................................................................... 328 18.3 Modes of operation....................................................................................................................................................... 329 18.4 Memory map/register definition................................................................................................................................... 330 18.4.1 TCD memory................................................................................................................................................. 330 18.4.2 TCD initialization.......................................................................................................................................... 330 18.4.3 TCD structure.................................................................................................................................................330 18.4.4 Reserved memory and bit fields.....................................................................................................................331 18.4.5 DMA register descriptions............................................................................................................................. 331 18.5 Functional description...................................................................................................................................................380 18.5.1 eDMA basic data flow................................................................................................................................... 380 18.5.2 Fault reporting and handling.......................................................................................................................... 383 18.5.3 Channel preemption....................................................................................................................................... 386 18.6 Initialization/application information........................................................................................................................... 386 18.6.1 eDMA initialization....................................................................................................................................... 386 18.6.2 Programming errors....................................................................................................................................... 388 18.6.3 Arbitration mode considerations....................................................................................................................389 S32K1xx Series Reference Manual, Rev. 9, 09/2018 12 NXP Semiconductors Section number Title Page 18.6.4 Performing DMA transfers............................................................................................................................ 389 18.6.5 Monitoring transfer descriptor status............................................................................................................. 393 18.6.6 Channel Linking.............................................................................................................................................395 18.6.7 Dynamic programming.................................................................................................................................. 396 18.6.8 Suspend/resume a DMA channel with active hardware service requests......................................................400 Chapter 19 Trigger MUX Control (TRGMUX) 19.1 Chip-specific TRGMUX information...........................................................................................................................403 19.1.1 Module interconnectivity............................................................................................................................... 403 19.1.2 TRGMUX register information..................................................................................................................... 407 19.2 Introduction...................................................................................................................................................................407 19.3 Features.........................................................................................................................................................................407 19.4 Memory map and register definition.............................................................................................................................408 19.4.1 TRGMUX register descriptions..................................................................................................................... 408 Chapter 20 External Watchdog Monitor (EWM) 20.1 Chip-specific EWM information ................................................................................................................................. 447 20.1.1 EWM_OUT signal configuration...................................................................................................................447 20.1.2 EWM Memory Map access............................................................................................................................447 20.1.3 EWM low-power modes................................................................................................................................ 447 20.2 Introduction...................................................................................................................................................................447 20.2.1 Features.......................................................................................................................................................... 448 20.2.2 Modes of Operation....................................................................................................................................... 448 20.2.3 Block Diagram............................................................................................................................................... 449 20.3 EWM Signal Descriptions............................................................................................................................................ 450 20.4 Memory Map/Register Definition.................................................................................................................................451 20.4.1 EWM register descriptions.............................................................................................................................451 20.5 Functional Description..................................................................................................................................................456 20.5.1 The EWM_OUT_b Signal............................................................................................................................. 456 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 13 Section number Title Page 20.5.2 EWM_OUT_b pin state in low power modes................................................................................................457 20.5.3 The EWM_in Signal...................................................................................................................................... 457 20.5.4 EWM Counter................................................................................................................................................ 458 20.5.5 EWM Compare Registers.............................................................................................................................. 458 20.5.6 EWM Refresh Mechanism.............................................................................................................................458 20.5.7 EWM Interrupt...............................................................................................................................................459 20.5.8 Counter clock prescaler..................................................................................................................................459 Chapter 21 Error Injection Module (EIM) 21.1 Chip-specific EIM information.....................................................................................................................................461 21.1.1 EIM channel assignments.............................................................................................................................. 461 21.2 Introduction...................................................................................................................................................................461 21.2.1 Overview........................................................................................................................................................461 21.2.2 Features.......................................................................................................................................................... 463 21.3 EIM register descriptions..............................................................................................................................................463 21.3.1 EIM Memory map..........................................................................................................................................464 21.3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 464 21.3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 465 21.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................468 21.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................470 21.4 Functional description...................................................................................................................................................471 21.4.1 Error injection scenarios................................................................................................................................ 471 Chapter 22 Error Reporting Module (ERM) 22.1 Chip-specific ERM information................................................................................................................................... 473 22.1.1 Sources of memory error events.................................................................................................................... 473 22.2 Introduction...................................................................................................................................................................473 22.2.1 Overview........................................................................................................................................................473 22.2.2 Features.......................................................................................................................................................... 474 S32K1xx Series Reference Manual, Rev. 9, 09/2018 14 NXP Semiconductors Section number Title Page 22.3 ERM register descriptions.............................................................................................................................................474 22.3.1 ERM Memory map........................................................................................................................................ 474 22.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 475 22.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 477 22.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 479 22.4 Functional description...................................................................................................................................................480 22.4.1 Single-bit correction events........................................................................................................................... 480 22.4.2 Non-correctable error events..........................................................................................................................481 22.5 Initialization.................................................................................................................................................................. 482 Chapter 23 Watchdog timer (WDOG) 23.1 Chip-specific WDOG information................................................................................................................................483 23.1.1 WDOG clocks................................................................................................................................................ 483 23.1.2 WDOG low-power modes............................................................................................................................. 483 23.1.3 Default watchdog timeout .............................................................................................................................484 23.2 Introduction...................................................................................................................................................................484 23.2.1 Features.......................................................................................................................................................... 484 23.2.2 Block diagram................................................................................................................................................ 485 23.3 Memory map and register definition.............................................................................................................................486 23.3.1 WDOG register descriptions..........................................................................................................................486 23.4 Functional description...................................................................................................................................................492 23.4.1 Clock source...................................................................................................................................................492 23.4.2 Watchdog refresh mechanism........................................................................................................................493 23.4.3 Configuring the Watchdog.............................................................................................................................495 23.4.4 Using interrupts to delay resets......................................................................................................................496 23.4.5 Backup reset...................................................................................................................................................496 23.4.6 Functionality in debug and low-power modes...............................................................................................497 23.4.7 Fast testing of the watchdog...........................................................................................................................497 23.5 Application Information................................................................................................................................................499 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 15 Section number Title Page 23.5.1 Disable Watchdog.......................................................................................................................................... 499 23.5.2 Disable Watchdog after Reset........................................................................................................................499 23.5.3 Configure Watchdog...................................................................................................................................... 500 23.5.4 Refreshing the Watchdog...............................................................................................................................500 Chapter 24 Cyclic Redundancy Check (CRC) 24.1 Chip-specific CRC information.................................................................................................................................... 501 24.2 Introduction...................................................................................................................................................................501 24.2.1 Features.......................................................................................................................................................... 501 24.2.2 Block diagram................................................................................................................................................ 502 24.2.3 Modes of operation........................................................................................................................................ 502 24.3 Memory map and register descriptions.........................................................................................................................502 24.3.1 CRC register descriptions.............................................................................................................................. 502 24.4 Functional description...................................................................................................................................................507 24.4.1 CRC initialization/reinitialization.................................................................................................................. 507 24.4.2 CRC calculations............................................................................................................................................507 24.4.3 Transpose feature........................................................................................................................................... 508 24.4.4 CRC result complement................................................................................................................................. 510 Chapter 25 Reset and Boot 25.1 Introduction...................................................................................................................................................................511 25.2 Reset..............................................................................................................................................................................511 25.2.1 Power-on reset (POR).................................................................................................................................... 512 25.2.2 System reset sources...................................................................................................................................... 512 25.2.3 MCU Resets................................................................................................................................................... 516 25.2.4 Reset pin ........................................................................................................................................................516 25.2.5 Debug resets...................................................................................................................................................517 25.3 Boot...............................................................................................................................................................................518 25.3.1 Boot sources...................................................................................................................................................518 S32K1xx Series Reference Manual, Rev. 9, 09/2018 16 NXP Semiconductors Section number Title Page 25.3.2 FOPT boot options......................................................................................................................................... 518 25.3.3 Boot sequence................................................................................................................................................ 519 Chapter 26 Reset Control Module (RCM) 26.1 Chip-specific RCM information................................................................................................................................... 521 26.1.1 RCM register information .............................................................................................................................521 26.2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 522 26.3 Introduction...................................................................................................................................................................522 26.4 Reset memory map and register descriptions............................................................................................................... 522 26.4.1 Version ID Register (RCM_VERID).............................................................................................................523 26.4.2 Parameter Register (RCM_PARAM)............................................................................................................ 524 26.4.3 System Reset Status Register (RCM_SRS)................................................................................................... 526 26.4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 529 26.4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................531 26.4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 533 Chapter 27 Clock Distribution 27.1 Introduction...................................................................................................................................................................537 27.2 High level clocking diagram.........................................................................................................................................537 27.3 Clock definitions...........................................................................................................................................................538 27.4 Internal clocking requirements..................................................................................................................................... 540 27.4.1 Clock divider values after reset......................................................................................................................544 27.4.2 HSRUN mode clocking................................................................................................................................. 544 27.4.3 VLPR mode clocking.....................................................................................................................................544 27.4.4 VLPR/VLPS mode entry............................................................................................................................... 544 27.5 Clock Gating................................................................................................................................................................. 545 27.6 Module clocks...............................................................................................................................................................545 Chapter 28 System Clock Generator (SCG) 28.1 Chip-specific SCG information.................................................................................................................................... 557 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 17 Section number Title Page 28.1.1 Supported frequency ranges...........................................................................................................................557 28.1.2 Oscillator and SPLL guidelines..................................................................................................................... 557 28.1.3 System clock switching .................................................................................................................................558 28.1.4 System clock and clock monitor requirement ...............................................................................................558 28.2 Introduction...................................................................................................................................................................559 28.2.1 Features.......................................................................................................................................................... 559 28.3 Memory Map/Register Definition.................................................................................................................................560 28.3.1 Version ID Register (SCG_VERID)..............................................................................................................561 28.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 562 28.3.3 Clock Status Register (SCG_CSR)................................................................................................................ 563 28.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................565 28.3.5 VLPR Clock Control Register (SCG_VCCR)............................................................................................... 567 28.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................569 28.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................571 28.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................573 28.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 575 28.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 576 28.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................578 28.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 579 28.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................580 28.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 581 28.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................583 28.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 584 28.3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 585 28.3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................587 28.3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 588 28.4 Functional description...................................................................................................................................................590 28.4.1 SCG Clock Mode Transitions........................................................................................................................ 590 Chapter 29 S32K1xx Series Reference Manual, Rev. 9, 09/2018 18 NXP Semiconductors Section number Title Page Peripheral Clock Controller (PCC) 29.1 Chip-specific PCC information.....................................................................................................................................593 29.1.1 PCC register information............................................................................................................................... 593 29.2 Introduction...................................................................................................................................................................596 29.3 Features.........................................................................................................................................................................596 29.4 Functional description...................................................................................................................................................597 29.5 Memory map and register definition.............................................................................................................................598 29.6 PCC register descriptions..............................................................................................................................................598 29.6.1 PCC Memory map......................................................................................................................................... 598 29.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 599 29.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 601 29.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 602 29.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 604 29.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 605 29.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................607 29.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 608 29.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................610 29.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................612 29.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................613 29.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................ 615 29.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................617 29.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................ 618 29.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................620 29.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 621 29.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 623 29.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 624 29.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................626 29.6.20 PCC RTC Register (PCC_RTC).................................................................................................................... 628 29.6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................629 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 19 Section number Title Page 29.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 631 29.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................633 29.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................634 29.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 636 29.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 637 29.6.27 PCC SAI0 Register (PCC_SAI0)...................................................................................................................639 29.6.28 PCC SAI1 Register (PCC_SAI1)...................................................................................................................640 29.6.29 PCC FlexIO Register (PCC_FlexIO).............................................................................................................642 29.6.30 PCC EWM Register (PCC_EWM)................................................................................................................ 643 29.6.31 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 645 29.6.32 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 646 29.6.33 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 648 29.6.34 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 649 29.6.35 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 651 29.6.36 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 653 29.6.37 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 654 29.6.38 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 656 29.6.39 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 658 29.6.40 PCC CMP0 Register (PCC_CMP0)...............................................................................................................659 29.6.41 PCC QSPI Register (PCC_QSPI).................................................................................................................. 661 29.6.42 PCC ENET Register (PCC_ENET)............................................................................................................... 663 Chapter 30 Clock Monitoring Unit (CMU) 30.1 CMU chip-specific information....................................................................................................................................665 30.2 Introduction...................................................................................................................................................................666 30.2.1 Basic operation...............................................................................................................................................667 30.2.2 Features.......................................................................................................................................................... 668 30.3 CMU_FC register descriptions..................................................................................................................................... 668 30.3.1 CMU_FC Memory map................................................................................................................................. 668 S32K1xx Series Reference Manual, Rev. 9, 09/2018 20 NXP Semiconductors Section number Title Page 30.3.2 Global Configuration Register (GCR)........................................................................................................... 669 30.3.3 Reference Count Configuration Register (RCCR).........................................................................................670 30.3.4 High Threshold Configuration Register (HTCR).......................................................................................... 671 30.3.5 Low Threshold Configuration Register (LTCR)........................................................................................... 672 30.3.6 Status Register (SR)....................................................................................................................................... 673 30.3.7 Interrupt Enable Register (IER)..................................................................................................................... 674 30.4 Functional description...................................................................................................................................................677 30.4.1 Monitored clock lost...................................................................................................................................... 677 30.5 Programming guidelines............................................................................................................................................... 677 30.5.1 Programming HFREF and LFREF................................................................................................................ 677 30.5.2 Programming RCCR[REF_CNT].................................................................................................................. 678 30.5.3 CMU_FC programming sequence................................................................................................................. 679 Chapter 31 Memories and Memory Interfaces 31.1 Introduction...................................................................................................................................................................681 31.2 Flash Memory Controller and flash memory modules................................................................................................. 681 31.3 SRAM configuration.....................................................................................................................................................682 31.3.1 SRAM sizes....................................................................................................................................................682 31.3.2 SRAM accessibility........................................................................................................................................683 31.3.3 SRAM arbitration and priority control...........................................................................................................684 31.3.4 SRAM retention: power modes and resets.....................................................................................................684 31.3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error.........................685 Chapter 32 PRAM Controller (PRAMC) 32.1 PRAMC chip-specific information ..............................................................................................................................687 32.2 Introduction...................................................................................................................................................................687 32.3 Memory map and register definition.............................................................................................................................688 32.4 Functional description...................................................................................................................................................688 32.4.1 Error Correcting Code (ECC)........................................................................................................................ 688 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 21 Section number Title Page 32.4.2 Read/Write introduction.................................................................................................................................689 32.4.3 Reads..............................................................................................................................................................689 32.4.4 Writes............................................................................................................................................................. 690 32.4.5 Late write hits.................................................................................................................................................691 32.5 Initialization / application information......................................................................................................................... 692 Chapter 33 Local Memory Controller (LMEM) 33.1 Chip-specific LMEM information ............................................................................................................................... 693 33.1.1 LMEM region description..............................................................................................................................693 33.1.2 LMEM SRAM sizes.......................................................................................................................................693 33.2 Introduction...................................................................................................................................................................693 33.2.1 Block Diagram............................................................................................................................................... 694 33.2.2 Cache features................................................................................................................................................ 695 33.3 Memory Map/Register Definition.................................................................................................................................697 33.3.1 LMEM register descriptions.......................................................................................................................... 697 33.4 Functional Description..................................................................................................................................................706 33.4.1 LMEM Function............................................................................................................................................ 706 33.4.2 SRAM Function............................................................................................................................................. 707 33.4.3 Cache Function.............................................................................................................................................. 709 33.4.4 Cache Control................................................................................................................................................ 710 Chapter 34 Miscellaneous System Control Module (MSCM) 34.1 Chip-specific MSCM information................................................................................................................................ 715 34.1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 715 34.1.2 Chip-specific register information................................................................................................................. 715 34.2 Overview.......................................................................................................................................................................716 34.3 Chip Configuration and Boot........................................................................................................................................716 34.4 MSCM Memory Map/Register Definition....................................................................................................................717 34.4.1 CPU Configuration Memory Map and Registers...........................................................................................717 S32K1xx Series Reference Manual, Rev. 9, 09/2018 22 NXP Semiconductors Section number Title Page 34.4.2 MSCM register descriptions.......................................................................................................................... 717 Chapter 35 Flash Memory Controller (FMC) 35.1 Chip-specific FMC information....................................................................................................................................749 35.1.1 FMC masters.................................................................................................................................................. 749 35.1.2 Program flash and Data flash port width....................................................................................................... 750 35.2 Introduction...................................................................................................................................................................750 35.2.1 Overview........................................................................................................................................................750 35.2.2 Features.......................................................................................................................................................... 750 35.3 Modes of operation....................................................................................................................................................... 751 35.4 External signal description............................................................................................................................................751 35.5 Functional description...................................................................................................................................................751 35.5.1 Default configuration..................................................................................................................................... 751 35.5.2 Speculative reads............................................................................................................................................752 35.6 Initialization and application information.....................................................................................................................753 Chapter 36 Flash Memory Module (FTFC) 36.1 Chip-specific FTFC information...................................................................................................................................755 36.1.1 Flash memory types....................................................................................................................................... 755 36.1.2 Flash memory sizes........................................................................................................................................756 36.1.3 Flash memory map.........................................................................................................................................775 36.1.4 Flash memory security................................................................................................................................... 776 36.1.5 Power mode restrictions on flash memory programming..............................................................................776 36.1.6 Flash memory modes..................................................................................................................................... 776 36.1.7 Erase all contents of flash memory................................................................................................................ 776 36.1.8 Customize MCU operations via FTFC_FOPT register..................................................................................777 36.1.9 Simultaneous operations on PFLASH read partitions .................................................................................. 777 36.2 Introduction...................................................................................................................................................................777 36.2.1 Features.......................................................................................................................................................... 778 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 23 Section number Title Page 36.2.2 Block diagram................................................................................................................................................ 780 36.2.3 Glossary......................................................................................................................................................... 781 36.3 External signal description............................................................................................................................................783 36.4 Memory map and registers............................................................................................................................................784 36.4.1 Flash configuration field description............................................................................................................. 784 36.4.2 Program flash 0 IFR map............................................................................................................................... 784 36.4.3 Data flash 0 IFR map..................................................................................................................................... 785 36.4.4 Register descriptions...................................................................................................................................... 786 36.5 Functional description...................................................................................................................................................804 36.5.1 Flash protection..............................................................................................................................................804 36.5.2 FlexNVM description.................................................................................................................................... 806 36.5.3 Interrupts........................................................................................................................................................ 809 36.5.4 Flash operation in low-power modes............................................................................................................. 810 36.5.5 Functional modes of operation.......................................................................................................................810 36.5.6 Flash memory reads and ignored writes........................................................................................................ 810 36.5.7 Read while write (RWW).............................................................................................................................. 811 36.5.8 Flash program and erase................................................................................................................................ 811 36.5.9 FTFC command operations............................................................................................................................811 36.5.10 Margin read commands..................................................................................................................................818 36.5.11 Flash command descriptions..........................................................................................................................819 36.5.12 Security.......................................................................................................................................................... 845 36.5.13 Cryptographic Services Engine (CSEc).........................................................................................................847 36.5.14 Reset sequence............................................................................................................................................... 885 Chapter 37 Quad Serial Peripheral Interface (QuadSPI) 37.1 Chip-specific QuadSPI information..............................................................................................................................887 37.1.1 Overview........................................................................................................................................................887 37.1.2 Memory size requirement ............................................................................................................................. 887 37.1.3 QuadSPI register reset values........................................................................................................................ 887 S32K1xx Series Reference Manual, Rev. 9, 09/2018 24 NXP Semiconductors Section number Title Page 37.1.4 Use case..........................................................................................................................................................888 37.1.5 Supported read modes....................................................................................................................................888 37.1.6 External memory options............................................................................................................................... 889 37.1.7 Recommended software configuration.......................................................................................................... 889 37.1.8 Recommended programming sequence......................................................................................................... 890 37.1.9 Clock ratio between QuadSPI clocks ............................................................................................................890 37.1.10 QuadSPI_MCR[SCLKCFG] implementation ...............................................................................................890 37.1.11 QuadSPI_SOCCR[SOCCFG] implementation .............................................................................................891 37.2 Introduction...................................................................................................................................................................893 37.2.1 Features.......................................................................................................................................................... 893 37.2.2 Block Diagram............................................................................................................................................... 894 37.2.3 QuadSPI Modes of Operation........................................................................................................................ 895 37.2.4 Acronyms and Abbreviations.........................................................................................................................896 37.2.5 Glossary for QuadSPI module....................................................................................................................... 896 37.3 External Signal Description.......................................................................................................................................... 898 37.3.1 Driving External Signals................................................................................................................................899 37.4 Memory Map and Register Definition..........................................................................................................................901 37.4.1 Register Write Access....................................................................................................................................901 37.4.2 Peripheral Bus Register Descriptions............................................................................................................ 902 37.4.3 Serial Flash Address Assignment.................................................................................................................. 945 37.5 Flash memory mapped AMBA bus.............................................................................................................................. 946 37.5.1 AHB Bus Access Considerations...................................................................................................................947 37.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A.....................................................947 37.5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B..................................................... 948 37.5.4 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).......................................................................... 949 37.6 Interrupt Signals............................................................................................................................................................951 37.7 Functional Description..................................................................................................................................................952 37.7.1 Serial Flash Access Schemes......................................................................................................................... 952 37.7.2 Normal Mode................................................................................................................................................. 952 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 25 Section number Title Page 37.7.3 HyperRAM Support.......................................................................................................................................971 37.8 Initialization/Application Information..........................................................................................................................972 37.8.1 Power Up and Reset.......................................................................................................................................972 37.8.2 Available Status/Flag Information................................................................................................................. 972 37.8.3 Flash Device Selection...................................................................................................................................975 37.8.4 DMA Usage................................................................................................................................................... 975 37.9 Byte Ordering - Endianness..........................................................................................................................................979 37.9.1 Programming Flash Data............................................................................................................................... 980 37.9.2 Reading Flash Data into the RX Buffer......................................................................................................... 980 37.9.3 Reading Flash Data into the AHB Buffer...................................................................................................... 981 37.10 Driving Flash Control Signals in Single and Dual Mode............................................................................................. 982 37.11 Serial Flash Devices......................................................................................................................................................982 37.11.1 Example Sequences........................................................................................................................................982 37.12 Sampling of Serial Flash Input Data.............................................................................................................................988 37.12.1 Basic Description........................................................................................................................................... 988 37.12.2 Supported read modes....................................................................................................................................989 37.12.3 Data Strobe (DQS) sampling method............................................................................................................ 992 37.13 Data Input Hold Requirement of Flash.........................................................................................................................995 Chapter 38 Power Management 38.1 Introduction...................................................................................................................................................................997 38.2 Power modes description.............................................................................................................................................. 997 38.3 Entering and exiting power modes............................................................................................................................... 999 38.4 Clocking modes............................................................................................................................................................ 999 38.4.1 Clock gating................................................................................................................................................... 999 38.4.2 Stop mode options..........................................................................................................................................999 38.4.3 DMA wake-up................................................................................................................................................1000 38.4.4 Compute Operation (CPO).............................................................................................................................1001 38.4.5 Peripheral Doze..............................................................................................................................................1002 S32K1xx Series Reference Manual, Rev. 9, 09/2018 26 NXP Semiconductors Section number Title Page 38.5 Power mode transitions.................................................................................................................................................1003 38.6 Shutdown sequencing for power modes....................................................................................................................... 1004 38.7 Power mode restrictions on flash memory programming.............................................................................................1004 38.8 Module operation in available power modes................................................................................................................1005 38.9 QuadSPI, Ethernet, and SAI operation ........................................................................................................................ 1009 Chapter 39 System Mode Controller (SMC) 39.1 Introduction...................................................................................................................................................................1011 39.2 Modes of operation....................................................................................................................................................... 1011 39.3 Memory map and register descriptions.........................................................................................................................1013 39.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................1014 39.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 1015 39.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................1016 39.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................1017 39.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................1019 39.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 1021 39.4 Functional description...................................................................................................................................................1021 39.4.1 Power mode transitions..................................................................................................................................1022 39.4.2 Power mode entry/exit sequencing................................................................................................................ 1023 39.4.3 Run modes......................................................................................................................................................1026 39.4.4 Stop modes.....................................................................................................................................................1028 39.4.5 Debug in low power modes........................................................................................................................... 1029 Chapter 40 Power Management Controller (PMC) 40.1 Chip-specific PMC information....................................................................................................................................1031 40.1.1 Modes supported............................................................................................................................................ 1031 40.2 Introduction...................................................................................................................................................................1031 40.3 Features.........................................................................................................................................................................1031 40.4 Modes of Operation...................................................................................................................................................... 1032 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 27 Section number Title Page 40.4.1 Full Performance Mode (FPM)......................................................................................................................1032 40.4.2 Low Power Mode (LPM)...............................................................................................................................1032 40.5 Low Voltage Detect (LVD) System............................................................................................................................. 1032 40.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 1033 40.5.2 LVD Interrupt Operation............................................................................................................................... 1033 40.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 1033 40.6 Memory Map and Register Definition..........................................................................................................................1033 40.6.1 PMC register descriptions..............................................................................................................................1033 Chapter 41 ADC Configuration 41.1 Instantiation information...............................................................................................................................................1041 41.1.1 Number of ADC channels..............................................................................................................................1041 41.1.2 ADC Connections/Channel Assignment........................................................................................................1042 41.2 Register implementation............................................................................................................................................... 1043 41.3 DMA Support on ADC................................................................................................................................................. 1043 41.4 ADC Hardware Interleaved Channels.......................................................................................................................... 1044 41.5 ADC internal supply monitoring.................................................................................................................................. 1045 41.6 ADC Reference Options............................................................................................................................................... 1045 41.7 ADC Trigger Sources................................................................................................................................................... 1045 41.7.1 PDB triggering scheme.................................................................................................................................. 1047 41.7.2 TRGMUX trigger scheme..............................................................................................................................1048 41.8 Trigger Selection...........................................................................................................................................................1049 41.9 Trigger Latching and Arbitration..................................................................................................................................1050 41.10 ADC triggering configurations .................................................................................................................................... 1052 41.11 ADC low-power modes................................................................................................................................................ 1059 41.12 ADC Trigger Concept – Use Case................................................................................................................................1059 41.13 ADC calibration scheme...............................................................................................................................................1061 41.14 S32K11X to S32K14X difference ............................................................................................................................... 1062 Chapter 42 S32K1xx Series Reference Manual, Rev. 9, 09/2018 28 NXP Semiconductors Section number Title Page Analog-to-Digital Converter (ADC) 42.1 Chip-specific ADC information....................................................................................................................................1063 42.2 Introduction...................................................................................................................................................................1063 42.2.1 Features.......................................................................................................................................................... 1063 42.2.2 Block diagram................................................................................................................................................ 1064 42.3 ADC signal descriptions............................................................................................................................................... 1065 42.3.1 Analog Power (VDDA)................................................................................................................................. 1065 42.3.2 Analog Ground (VSSA).................................................................................................................................1065 42.3.3 Voltage Reference Select............................................................................................................................... 1065 42.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 1066 42.4 ADC register descriptions.............................................................................................................................................1066 42.4.1 ADC Memory map.........................................................................................................................................1066 42.4.2 ADC Status and Control Register 1 (SC1A - aSC1P)................................................................................... 1068 42.4.3 ADC Configuration Register 1 (CFG1)......................................................................................................... 1071 42.4.4 ADC Configuration Register 2 (CFG2)......................................................................................................... 1073 42.4.5 ADC Data Result Registers (RA - aRP)........................................................................................................ 1074 42.4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 1076 42.4.7 Status and Control Register 2 (SC2).............................................................................................................. 1077 42.4.8 Status and Control Register 3 (SC3).............................................................................................................. 1080 42.4.9 BASE Offset Register (BASE_OFS).............................................................................................................1081 42.4.10 ADC Offset Correction Register (OFS).........................................................................................................1082 42.4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 1083 42.4.12 ADC X Offset Correction Register (XOFS).................................................................................................. 1084 42.4.13 ADC Y Offset Correction Register (YOFS).................................................................................................. 1085 42.4.14 ADC Gain Register (G)..................................................................................................................................1086 42.4.15 ADC User Gain Register (UG)...................................................................................................................... 1088 42.4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 1089 42.4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 1090 42.4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 1091 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 29 Section number Title Page 42.4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 1091 42.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 1092 42.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................1093 42.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 1094 42.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS).................................................................1095 42.4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS)................................................. 1096 42.4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS)................................................. 1097 42.4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS)................................................. 1098 42.4.27 ADC Plus-Side General Calibration Offset Value Register 0 (CLP0_OFS)................................................. 1099 42.4.28 ADC Plus-Side General Calibration Offset Value Register X (CLPX_OFS)............................................... 1100 42.4.29 ADC Plus-Side General Calibration Offset Value Register 9 (CLP9_OFS)................................................. 1101 42.4.30 ADC Status and Control Register 1 (SC1AA - SC1Z).................................................................................. 1102 42.4.31 ADC Data Result Registers (RAA - RZ)....................................................................................................... 1105 42.5 Functional description...................................................................................................................................................1107 42.5.1 Clock select and divide control......................................................................................................................1107 42.5.2 Voltage reference selection............................................................................................................................1108 42.5.3 Hardware trigger and channel selects............................................................................................................ 1108 42.5.4 Conversion control.........................................................................................................................................1109 42.5.5 Automatic compare function..........................................................................................................................1113 42.5.6 Calibration function....................................................................................................................................... 1114 42.5.7 User-defined offset function.......................................................................................................................... 1115 42.5.8 MCU Normal Stop mode operation............................................................................................................... 1116 Chapter 43 Comparator (CMP) 43.1 Chip-specific CMP information....................................................................................................................................1117 43.1.1 Instantiation information................................................................................................................................1117 43.1.2 CMP input connections..................................................................................................................................1117 43.1.3 CMP external references................................................................................................................................1119 43.1.4 External window/sample input.......................................................................................................................1119 S32K1xx Series Reference Manual, Rev. 9, 09/2018 30 NXP Semiconductors Section number Title Page 43.1.5 CMP trigger mode..........................................................................................................................................1119 43.1.6 Programming recommendation......................................................................................................................1120 43.1.7 S32K11X to S32K14X difference ................................................................................................................ 1120 43.2 Introduction...................................................................................................................................................................1121 43.3 Features.........................................................................................................................................................................1121 43.3.1 CMP features..................................................................................................................................................1121 43.3.2 8-bit DAC key features.................................................................................................................................. 1122 43.3.3 ANMUX key features.................................................................................................................................... 1122 43.4 CMP, DAC, and ANMUX diagram..............................................................................................................................1123 43.5 CMP block diagram...................................................................................................................................................... 1124 43.6 CMP pin descriptions....................................................................................................................................................1126 43.6.1 External pins.................................................................................................................................................. 1126 43.7 CMP functional modes................................................................................................................................................. 1127 43.7.1 Disabled mode (# 1).......................................................................................................................................1128 43.7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 1129 43.7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 1129 43.7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 1131 43.7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 1133 43.7.6 Windowed/Resampled mode (# 6).................................................................................................................1135 43.7.7 Windowed/Filtered mode (#7)....................................................................................................................... 1136 43.8 Memory map/register definitions..................................................................................................................................1137 43.8.1 CMP Control Register 0 (CMP_C0)..............................................................................................................1137 43.8.2 CMP Control Register 1 (CMP_C1)..............................................................................................................1141 43.8.3 CMP Control Register 2 (CMP_C2)..............................................................................................................1144 43.9 CMP functional description.......................................................................................................................................... 1146 43.9.1 Initialization................................................................................................................................................... 1146 43.9.2 Low-pass filter............................................................................................................................................... 1147 43.10 Interrupts.......................................................................................................................................................................1149 43.11 DMA support................................................................................................................................................................ 1149 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 31 Section number Title Page 43.12 DAC functional description.......................................................................................................................................... 1150 43.12.1 Digital-to-analog converter block diagram.................................................................................................... 1150 43.12.2 DAC resets..................................................................................................................................................... 1150 43.12.3 DAC clocks.................................................................................................................................................... 1151 43.12.4 DAC interrupts...............................................................................................................................................1151 43.13 Trigger mode.................................................................................................................................................................1151 Chapter 44 Programmable delay block (PDB) 44.1 Chip-specific PDB information.................................................................................................................................... 1155 44.1.1 Instantiation Information................................................................................................................................1155 44.1.2 PDB trigger interconnections with ADC and TRGMUX.............................................................................. 1156 44.1.3 Back-to-back acknowledgement connections................................................................................................1156 44.1.4 Pulse-Out Enable Register Implementation...................................................................................................1163 44.1.5 S32K11X to S32K14X difference ................................................................................................................ 1163 44.2 Introduction...................................................................................................................................................................1163 44.2.1 Features.......................................................................................................................................................... 1163 44.2.2 Implementation.............................................................................................................................................. 1164 44.2.3 Back-to-back acknowledgment connections..................................................................................................1165 44.2.4 Block diagram................................................................................................................................................ 1165 44.2.5 Modes of operation........................................................................................................................................ 1166 44.3 Memory map and register definition.............................................................................................................................1167 44.3.1 Status and Control register (PDB_SC)...........................................................................................................1169 44.3.2 Modulus register (PDB_MOD)......................................................................................................................1172 44.3.3 Counter register (PDB_CNT)........................................................................................................................ 1173 44.3.4 Interrupt Delay register (PDB_IDLY)........................................................................................................... 1173 44.3.5 Channel n Control register 1 (PDB_CHnC1)................................................................................................ 1174 44.3.6 Channel n Status register (PDB_CHnS)........................................................................................................ 1175 44.3.7 Channel n Delay 0 register (PDB_CHnDLY0)..............................................................................................1175 44.3.8 Channel n Delay 1 register (PDB_CHnDLY1)..............................................................................................1176 S32K1xx Series Reference Manual, Rev. 9, 09/2018 32 NXP Semiconductors Section number Title Page 44.3.9 Channel n Delay 2 register (PDB_CHnDLY2)..............................................................................................1177 44.3.10 Channel n Delay 3 register (PDB_CHnDLY3)..............................................................................................1177 44.3.11 Channel n Delay 4 register (PDB_CHnDLY4)..............................................................................................1178 44.3.12 Channel n Delay 5 register (PDB_CHnDLY5)..............................................................................................1179 44.3.13 Channel n Delay 6 register (PDB_CHnDLY6)..............................................................................................1179 44.3.14 Channel n Delay 7 register (PDB_CHnDLY7)..............................................................................................1180 44.3.15 Pulse-Out n Enable register (PDB_POEN)....................................................................................................1180 44.3.16 Pulse-Out n Delay register (PDB_POnDLY)................................................................................................ 1181 44.4 Functional description...................................................................................................................................................1181 44.4.1 PDB pre-trigger and trigger outputs...............................................................................................................1181 44.4.2 PDB trigger input source selection................................................................................................................ 1184 44.4.3 Pulse-Out's..................................................................................................................................................... 1184 44.4.4 Updating the delay registers...........................................................................................................................1185 44.4.5 Interrupts........................................................................................................................................................ 1187 44.4.6 DMA.............................................................................................................................................................. 1187 44.5 Application information................................................................................................................................................1187 44.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 1187 Chapter 45 FlexTimer Module (FTM) 45.1 Chip-specific FTM information....................................................................................................................................1189 45.1.1 Instantiation Information................................................................................................................................1189 45.1.2 FTM Interrupts...............................................................................................................................................1190 45.1.3 FTM Fault Detection Inputs...........................................................................................................................1190 45.1.4 FTM Hardware Triggers and Synchronization.............................................................................................. 1192 45.1.5 FTM Input Capture Options...........................................................................................................................1194 45.1.6 FTM Hall sensor support............................................................................................................................... 1195 45.1.7 FTM Modulation Implementation................................................................................................................. 1195 45.1.8 FTM Global Time Base................................................................................................................................. 1196 45.1.9 FTM BDM and debug halt mode...................................................................................................................1197 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 33 Section number Title Page 45.1.10 S32K11X to S32K14X difference ................................................................................................................ 1197 45.2 Introduction...................................................................................................................................................................1199 45.2.1 Features.......................................................................................................................................................... 1199 45.2.2 Modes of operation........................................................................................................................................ 1200 45.2.3 Block Diagram............................................................................................................................................... 1201 45.3 FTM signal descriptions............................................................................................................................................... 1203 45.4 Memory map and register definition.............................................................................................................................1203 45.4.1 Memory map.................................................................................................................................................. 1203 45.4.2 Register descriptions...................................................................................................................................... 1204 45.4.3 FTM register descriptions.............................................................................................................................. 1204 45.5 Functional Description..................................................................................................................................................1261 45.5.1 Clock source...................................................................................................................................................1261 45.5.2 Prescaler......................................................................................................................................................... 1261 45.5.3 Counter...........................................................................................................................................................1262 45.5.4 Channel Modes.............................................................................................................................................. 1268 45.5.5 Input Capture Mode....................................................................................................................................... 1270 45.5.6 Output Compare mode................................................................................................................................... 1275 45.5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 1276 45.5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 1278 45.5.9 Combine mode............................................................................................................................................... 1280 45.5.10 Modified Combine PWM Mode.................................................................................................................... 1288 45.5.11 Complementary Mode....................................................................................................................................1291 45.5.12 Registers updated from write buffers.............................................................................................................1293 45.5.13 PWM synchronization....................................................................................................................................1294 45.5.14 Inverting......................................................................................................................................................... 1310 45.5.15 Software Output Control Mode......................................................................................................................1311 45.5.16 Deadtime insertion......................................................................................................................................... 1313 45.5.17 Output mask................................................................................................................................................... 1317 45.5.18 Fault Control.................................................................................................................................................. 1318 S32K1xx Series Reference Manual, Rev. 9, 09/2018 34 NXP Semiconductors Section number Title Page 45.5.19 Polarity Control..............................................................................................................................................1322 45.5.20 Initialization................................................................................................................................................... 1323 45.5.21 Features Priority.............................................................................................................................................1323 45.5.22 External Trigger............................................................................................................................................. 1324 45.5.23 Initialization Trigger...................................................................................................................................... 1325 45.5.24 Capture Test Mode.........................................................................................................................................1327 45.5.25 DMA.............................................................................................................................................................. 1328 45.5.26 Dual Edge Capture Mode...............................................................................................................................1329 45.5.27 Quadrature Decoder Mode.............................................................................................................................1337 45.5.28 Debug mode................................................................................................................................................... 1343 45.5.29 Reload Points................................................................................................................................................. 1344 45.5.30 Global Load....................................................................................................................................................1347 45.5.31 Global time base (GTB).................................................................................................................................1348 45.5.32 Channel trigger output................................................................................................................................... 1349 45.5.33 External Control of Channels Output.............................................................................................................1350 45.5.34 Dithering........................................................................................................................................................ 1350 45.6 Reset Overview.............................................................................................................................................................1361 45.7 FTM Interrupts..............................................................................................................................................................1363 45.7.1 Timer Overflow Interrupt...............................................................................................................................1363 45.7.2 Reload Point Interrupt....................................................................................................................................1363 45.7.3 Channel (n) Interrupt......................................................................................................................................1363 45.7.4 Fault Interrupt................................................................................................................................................ 1363 45.8 Initialization Procedure.................................................................................................................................................1364 Chapter 46 Low Power Interrupt Timer (LPIT) 46.1 Chip-specific LPIT information....................................................................................................................................1367 46.1.1 Instantiation Information................................................................................................................................1367 46.1.2 LPIT/DMA Periodic Trigger Assignments ...................................................................................................1367 46.1.3 LPIT input triggers ........................................................................................................................................1368 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 35 Section number Title Page 46.1.4 LPIT/ADC Trigger.........................................................................................................................................1368 46.1.5 S32K11X to S32K14X difference ................................................................................................................ 1369 46.2 Introduction...................................................................................................................................................................1370 46.2.1 Overview........................................................................................................................................................1370 46.2.2 Block Diagram............................................................................................................................................... 1371 46.3 Modes of operation....................................................................................................................................................... 1372 46.4 Memory Map and Registers..........................................................................................................................................1373 46.4.1 LPIT register descriptions..............................................................................................................................1373 46.5 Functional description...................................................................................................................................................1389 46.5.1 LPIT programming model............................................................................................................................. 1389 46.5.2 Initialization................................................................................................................................................... 1391 46.5.3 Timer Modes.................................................................................................................................................. 1392 46.5.4 Trigger Control for Timers............................................................................................................................ 1392 46.5.5 Channel Chaining...........................................................................................................................................1393 46.5.6 Detailed timing...............................................................................................................................................1394 Chapter 47 Low Power Timer (LPTMR) 47.1 Chip-specific LPTMR information...............................................................................................................................1407 47.1.1 Instantiation Information................................................................................................................................1407 47.1.2 LPTMR pulse counter input options..............................................................................................................1407 47.1.3 S32K11X to S32K14X difference ................................................................................................................ 1408 47.2 Introduction...................................................................................................................................................................1408 47.2.1 Features.......................................................................................................................................................... 1408 47.2.2 Modes of operation........................................................................................................................................ 1408 47.3 LPTMR signal descriptions.......................................................................................................................................... 1409 47.3.1 Detailed signal descriptions........................................................................................................................... 1409 47.4 Memory map and register definition.............................................................................................................................1410 47.4.1 LPTMR register descriptions......................................................................................................................... 1410 47.5 Functional description...................................................................................................................................................1415 S32K1xx Series Reference Manual, Rev. 9, 09/2018 36 NXP Semiconductors Section number Title Page 47.5.1 LPTMR power and reset................................................................................................................................ 1415 47.5.2 LPTMR clocking............................................................................................................................................1416 47.5.3 LPTMR prescaler/glitch filter........................................................................................................................1416 47.5.4 LPTMR counter............................................................................................................................................. 1417 47.5.5 LPTMR compare............................................................................................................................................1418 47.5.6 LPTMR interrupt............................................................................................................................................1418 47.5.7 LPTMR hardware trigger...............................................................................................................................1419 Chapter 48 Real Time Clock (RTC) 48.1 Chip-specific RTC information.................................................................................................................................... 1421 48.1.1 RTC instantiation........................................................................................................................................... 1421 48.1.2 RTC interrupts ...............................................................................................................................................1421 48.1.3 Software recommendation............................................................................................................................. 1421 48.1.4 Multiple trigger ............................................................................................................................................. 1421 48.1.5 S32K11X to S32K14X difference ................................................................................................................ 1422 48.2 Introduction...................................................................................................................................................................1422 48.2.1 Features.......................................................................................................................................................... 1422 48.2.2 Modes of operation........................................................................................................................................ 1422 48.2.3 RTC signal descriptions................................................................................................................................. 1422 48.3 Register definition.........................................................................................................................................................1423 48.3.1 RTC register descriptions...............................................................................................................................1423 48.4 Functional description...................................................................................................................................................1434 48.4.1 Power, clocking, and reset............................................................................................................................. 1434 48.4.2 Time counter.................................................................................................................................................. 1435 48.4.3 Compensation.................................................................................................................................................1435 48.4.4 Time alarm..................................................................................................................................................... 1436 48.4.5 Update mode.................................................................................................................................................. 1437 48.4.6 Register lock.................................................................................................................................................. 1437 48.4.7 Interrupt..........................................................................................................................................................1437 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 37 Section number Title Page Chapter 49 Low Power Serial Peripheral Interface (LPSPI) 49.1 Chip-specific LPSPI information..................................................................................................................................1439 49.1.1 Instantiation Information................................................................................................................................1439 49.2 Introduction...................................................................................................................................................................1440 49.2.1 Features.......................................................................................................................................................... 1442 49.2.2 Block Diagram............................................................................................................................................... 1442 49.2.3 Modes of operation........................................................................................................................................ 1443 49.2.4 Signal Descriptions........................................................................................................................................ 1443 49.2.5 Wiring options................................................................................................................................................1444 49.3 Memory Map and Registers..........................................................................................................................................1446 49.3.1 LPSPI register descriptions............................................................................................................................1446 49.4 Functional description...................................................................................................................................................1469 49.4.1 Clocking and resets........................................................................................................................................ 1469 49.4.2 Master Mode.................................................................................................................................................. 1470 49.4.3 Slave Mode.................................................................................................................................................... 1476 49.4.4 Interrupts and DMA Requests........................................................................................................................1478 49.4.5 Peripheral Triggers.........................................................................................................................................1479 Chapter 50 Low Power Inter-Integrated Circuit (LPI2C) 50.1 Chip-specific LPI2C information................................................................................................................................. 1481 50.1.1 Instantiation information................................................................................................................................1481 50.2 Introduction...................................................................................................................................................................1482 50.2.1 Features.......................................................................................................................................................... 1483 50.2.2 Block Diagram............................................................................................................................................... 1485 50.2.3 Modes of operation........................................................................................................................................ 1485 50.2.4 Signal Descriptions........................................................................................................................................ 1485 50.2.5 Wiring options................................................................................................................................................1486 50.3 Memory Map and Registers..........................................................................................................................................1487 S32K1xx Series Reference Manual, Rev. 9, 09/2018 38 NXP Semiconductors Section number Title Page 50.3.1 LPI2C register descriptions............................................................................................................................1488 50.4 Functional description...................................................................................................................................................1526 50.4.1 Clocking and Resets.......................................................................................................................................1526 50.4.2 Master Mode.................................................................................................................................................. 1527 50.4.3 Slave Mode.................................................................................................................................................... 1533 50.4.4 Interrupts and DMA Requests........................................................................................................................1535 50.4.5 Peripheral Triggers.........................................................................................................................................1537 Chapter 51 Low Power Universal Asynchronous Receiver/Transmitter (LPUART) 51.1 Chip-specific LPUART information.............................................................................................................................1539 51.1.1 Instantiation Information................................................................................................................................1539 51.2 Introduction...................................................................................................................................................................1540 51.2.1 Features.......................................................................................................................................................... 1540 51.2.2 Modes of operation........................................................................................................................................ 1541 51.2.3 Signal Descriptions........................................................................................................................................ 1541 51.2.4 Block diagram................................................................................................................................................ 1541 51.3 Register definition.........................................................................................................................................................1543 51.3.1 LPUART register descriptions.......................................................................................................................1543 51.4 Functional description...................................................................................................................................................1569 51.4.1 Clocking and Resets.......................................................................................................................................1569 51.4.2 Baud rate generation...................................................................................................................................... 1569 51.4.3 Transmitter functional description................................................................................................................. 1570 51.4.4 Receiver functional description..................................................................................................................... 1574 51.4.5 Additional LPUART functions...................................................................................................................... 1580 51.4.6 Infrared interface............................................................................................................................................1582 51.4.7 Interrupts and status flags.............................................................................................................................. 1583 51.4.8 Peripheral Triggers.........................................................................................................................................1584 Chapter 52 Flexible I/O (FlexIO) S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 39 Section number Title Page 52.1 Chip-specific FlexIO information.................................................................................................................................1587 52.1.1 FlexIO Configuration.....................................................................................................................................1587 52.2 Introduction...................................................................................................................................................................1587 52.2.1 Overview........................................................................................................................................................1587 52.2.2 Features.......................................................................................................................................................... 1588 52.2.3 Block Diagram............................................................................................................................................... 1588 52.2.4 Modes of operation........................................................................................................................................ 1589 52.2.5 FlexIO Signal Descriptions............................................................................................................................1589 52.3 Memory Map and Registers..........................................................................................................................................1590 52.3.1 FLEXIO register descriptions........................................................................................................................ 1590 52.4 Functional description...................................................................................................................................................1614 52.4.1 Clocking and Resets.......................................................................................................................................1614 52.4.2 Shifter operation.............................................................................................................................................1615 52.4.3 Timer Operation.............................................................................................................................................1617 52.4.4 Pin operation.................................................................................................................................................. 1621 52.4.5 Interrupts and DMA Requests........................................................................................................................1622 52.4.6 Peripheral Triggers.........................................................................................................................................1622 52.5 Application Information................................................................................................................................................1623 52.5.1 UART Transmit............................................................................................................................................. 1623 52.5.2 UART Receive...............................................................................................................................................1624 52.5.3 SPI Master......................................................................................................................................................1626 52.5.4 SPI Slave........................................................................................................................................................ 1628 52.5.5 I2C Master......................................................................................................................................................1629 52.5.6 I2S Master...................................................................................................................................................... 1631 52.5.7 I2S Slave........................................................................................................................................................ 1633 Chapter 53 FlexCAN 53.1 Chip-specific FlexCAN information.............................................................................................................................1635 53.1.1 Instantiation information................................................................................................................................1635 S32K1xx Series Reference Manual, Rev. 9, 09/2018 40 NXP Semiconductors Section number Title Page 53.1.2 Reset value of MDIS bit.................................................................................................................................1636 53.1.3 FlexCAN external time tick .......................................................................................................................... 1636 53.1.4 FlexCAN Interrupts........................................................................................................................................1636 53.1.5 FlexCAN Operation in Low Power Modes....................................................................................................1637 53.1.6 FlexCAN oscillator clock...............................................................................................................................1637 53.1.7 Supported baud rate ...................................................................................................................................... 1637 53.1.8 Requirements for entering FlexCAN modes: Freeze, Disable, Stop............................................................. 1637 53.2 Introduction...................................................................................................................................................................1639 53.2.1 Overview........................................................................................................................................................1640 53.2.2 FlexCAN module features............................................................................................................................. 1641 53.2.3 Modes of operation........................................................................................................................................ 1642 53.3 FlexCAN signal descriptions........................................................................................................................................ 1644 53.3.1 CAN Rx .........................................................................................................................................................1644 53.3.2 CAN Tx .........................................................................................................................................................1645 53.4 Memory map/register definition................................................................................................................................... 1645 53.4.1 FlexCAN memory mapping...........................................................................................................................1645 53.4.2 CAN register descriptions..............................................................................................................................1646 53.4.3 Message buffer structure................................................................................................................................1717 53.4.4 FlexCAN memory partition for CAN FD...................................................................................................... 1724 53.4.5 FlexCAN message buffer memory map.........................................................................................................1725 53.4.6 Rx FIFO structure.......................................................................................................................................... 1727 53.5 Functional description...................................................................................................................................................1730 53.5.1 Transmit process............................................................................................................................................ 1730 53.5.2 Arbitration process.........................................................................................................................................1732 53.5.3 Receive process..............................................................................................................................................1735 53.5.4 Matching process........................................................................................................................................... 1738 53.5.5 Receive process under Pretended Networking mode.....................................................................................1742 53.5.6 Move process................................................................................................................................................. 1747 53.5.7 Data coherence...............................................................................................................................................1749 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 41 Section number Title Page 53.5.8 Rx FIFO......................................................................................................................................................... 1752 53.5.9 CAN protocol related features....................................................................................................................... 1755 53.5.10 Clock domains and restrictions...................................................................................................................... 1776 53.5.11 Modes of operation details.............................................................................................................................1780 53.5.12 Interrupts........................................................................................................................................................ 1784 53.5.13 Bus interface.................................................................................................................................................. 1785 53.6 Initialization/application information........................................................................................................................... 1786 53.6.1 FlexCAN initialization sequence................................................................................................................... 1786 Chapter 54 Synchronous Audio Interface (SAI) 54.1 Chip-specific SAI information .....................................................................................................................................1789 54.1.1 SAI configuration...........................................................................................................................................1789 54.1.2 Chip-specific register information................................................................................................................. 1790 54.2 Introduction...................................................................................................................................................................1791 54.2.1 Features.......................................................................................................................................................... 1791 54.2.2 Block diagram................................................................................................................................................ 1791 54.2.3 Modes of operation........................................................................................................................................ 1792 54.3 External signals.............................................................................................................................................................1793 54.4 Memory map and register definition.............................................................................................................................1793 54.4.1 I2S register descriptions.................................................................................................................................1793 54.5 Functional description...................................................................................................................................................1826 54.5.1 SAI clocking.................................................................................................................................................. 1826 54.5.2 SAI resets....................................................................................................................................................... 1828 54.5.3 Synchronous modes....................................................................................................................................... 1829 54.5.4 Frame sync configuration...............................................................................................................................1830 54.5.5 Data FIFO...................................................................................................................................................... 1830 54.5.6 Word mask register........................................................................................................................................ 1834 54.5.7 Interrupts and DMA requests.........................................................................................................................1835 Chapter 55 S32K1xx Series Reference Manual, Rev. 9, 09/2018 42 NXP Semiconductors Section number Title Page Ethernet MAC (ENET) 55.1 Chip-specific ENET information..................................................................................................................................1839 55.1.1 Software guideline during ENET operation...................................................................................................1839 55.2 Introduction...................................................................................................................................................................1839 55.3 Overview.......................................................................................................................................................................1840 55.3.1 Features.......................................................................................................................................................... 1840 55.3.2 Block diagram................................................................................................................................................ 1843 55.4 External signal description............................................................................................................................................1843 55.5 Memory map/register definition................................................................................................................................... 1845 55.5.1 Interrupt Event Register (ENET_EIR)...........................................................................................................1850 55.5.2 Interrupt Mask Register (ENET_EIMR)........................................................................................................1853 55.5.3 Receive Descriptor Active Register (ENET_RDAR)....................................................................................1856 55.5.4 Transmit Descriptor Active Register (ENET_TDAR)...................................................................................1857 55.5.5 Ethernet Control Register (ENET_ECR).......................................................................................................1858 55.5.6 MII Management Frame Register (ENET_MMFR)...................................................................................... 1860 55.5.7 MII Speed Control Register (ENET_MSCR)................................................................................................ 1860 55.5.8 MIB Control Register (ENET_MIBC).......................................................................................................... 1863 55.5.9 Receive Control Register (ENET_RCR)....................................................................................................... 1864 55.5.10 Transmit Control Register (ENET_TCR)...................................................................................................... 1867 55.5.11 Physical Address Lower Register (ENET_PALR)........................................................................................ 1869 55.5.12 Physical Address Upper Register (ENET_PAUR)........................................................................................ 1869 55.5.13 Opcode/Pause Duration Register (ENET_OPD)........................................................................................... 1870 55.5.14 Descriptor Individual Upper Address Register (ENET_IAUR).................................................................... 1870 55.5.15 Descriptor Individual Lower Address Register (ENET_IALR).................................................................... 1871 55.5.16 Descriptor Group Upper Address Register (ENET_GAUR).........................................................................1871 55.5.17 Descriptor Group Lower Address Register (ENET_GALR).........................................................................1872 55.5.18 Transmit FIFO Watermark Register (ENET_TFWR)................................................................................... 1872 55.5.19 Receive Descriptor Ring Start Register (ENET_RDSR)...............................................................................1873 55.5.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR).................................................................. 1874 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 43 Section number Title Page 55.5.21 Maximum Receive Buffer Size Register (ENET_MRBR)............................................................................ 1875 55.5.22 Receive FIFO Section Full Threshold (ENET_RSFL).................................................................................. 1876 55.5.23 Receive FIFO Section Empty Threshold (ENET_RSEM)............................................................................ 1876 55.5.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)............................................................................ 1877 55.5.25 Receive FIFO Almost Full Threshold (ENET_RAFL)..................................................................................1877 55.5.26 Transmit FIFO Section Empty Threshold (ENET_TSEM)........................................................................... 1878 55.5.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM)...........................................................................1878 55.5.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)................................................................................ 1879 55.5.29 Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................... 1879 55.5.30 Frame Truncation Length (ENET_FTRL).....................................................................................................1880 55.5.31 Transmit Accelerator Function Configuration (ENET_TACC).................................................................... 1880 55.5.32 Receive Accelerator Function Configuration (ENET_RACC)......................................................................1881 55.5.33 Reserved Statistic Register (ENET_RMON_T_DROP)................................................................................1882 55.5.34 Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS)............................................................ 1883 55.5.35 Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)........................................................1883 55.5.36 Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)........................................................1884 55.5.37 Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN)............................ 1884 55.5.38 Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE)............1884 55.5.39 Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)..........1885 55.5.40 Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG).....................1885 55.5.41 Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)........ 1886 55.5.42 Tx Collision Count Statistic Register (ENET_RMON_T_COL).................................................................. 1886 55.5.43 Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................... 1886 55.5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)............................................ 1887 55.5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........................................ 1887 55.5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........................................ 1888 55.5.47 Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................... 1888 55.5.48 Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047)................................ 1889 55.5.49 Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048).......................... 1889 S32K1xx Series Reference Manual, Rev. 9, 09/2018 44 NXP Semiconductors Section number Title Page 55.5.50 Tx Octets Statistic Register (ENET_RMON_T_OCTETS).......................................................................... 1889 55.5.51 Reserved Statistic Register (ENET_IEEE_T_DROP)...................................................................................1890 55.5.52 Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK)................................................ 1890 55.5.53 Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................... 1891 55.5.54 Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).........................1891 55.5.55 Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)....................................1891 55.5.56 Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL).................................. 1892 55.5.57 Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL).....................1892 55.5.58 Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR)....................1893 55.5.59 Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)....................... 1893 55.5.60 Reserved Statistic Register (ENET_IEEE_T_SQE)...................................................................................... 1893 55.5.61 Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC)...............................1894 55.5.62 Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)...........1894 55.5.63 Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS)............................................................ 1895 55.5.64 Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)....................................................... 1895 55.5.65 Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)....................................................... 1895 55.5.66 Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)............................1896 55.5.67 Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (ENET_RMON_R_UNDERSIZE)................................................................................................................1896 55.5.68 Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE)...1897 55.5.69 Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................... 1897 55.5.70 Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)....... 1897 55.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0).........................................................................1898 55.5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)...................................................................1898 55.5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........................................... 1899 55.5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)....................................... 1899 55.5.75 Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)....................................... 1899 55.5.76 Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................... 1900 55.5.77 Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................... 1900 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 45 Section number Title Page 55.5.78 Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)........................... 1901 55.5.79 Rx Octets Statistic Register (ENET_RMON_R_OCTETS)..........................................................................1901 55.5.80 Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)................................................. 1901 55.5.81 Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................... 1902 55.5.82 Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC).............................................. 1902 55.5.83 Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN)................................ 1903 55.5.84 Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)..........................................1903 55.5.85 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)...................................1903 55.5.86 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK).........1904 55.5.87 Adjustable Timer Control Register (ENET_ATCR)..................................................................................... 1904 55.5.88 Timer Value Register (ENET_ATVR).......................................................................................................... 1906 55.5.89 Timer Offset Register (ENET_ATOFF)........................................................................................................ 1907 55.5.90 Timer Period Register (ENET_ATPER)........................................................................................................1907 55.5.91 Timer Correction Register (ENET_ATCOR)................................................................................................ 1908 55.5.92 Time-Stamping Clock Period Register (ENET_ATINC).............................................................................. 1908 55.5.93 Timestamp of Last Transmitted Frame (ENET_ATSTMP).......................................................................... 1909 55.5.94 Timer Global Status Register (ENET_TGSR)...............................................................................................1909 55.5.95 Timer Control Status Register (ENET_TCSRn)............................................................................................1910 55.5.96 Timer Compare Capture Register (ENET_TCCRn)......................................................................................1911 55.6 Functional description...................................................................................................................................................1912 55.6.1 Ethernet MAC frame formats........................................................................................................................ 1912 55.6.2 IP and higher layers frame format..................................................................................................................1915 55.6.3 IEEE 1588 message formats.......................................................................................................................... 1919 55.6.4 MAC receive.................................................................................................................................................. 1923 55.6.5 MAC transmit................................................................................................................................................ 1929 55.6.6 Full-duplex flow control operation................................................................................................................ 1933 55.6.7 Magic packet detection.................................................................................................................................. 1935 55.6.8 IP accelerator functions..................................................................................................................................1936 55.6.9 Resets and stop controls.................................................................................................................................1940 S32K1xx Series Reference Manual, Rev. 9, 09/2018 46 NXP Semiconductors Section number Title Page 55.6.10 IEEE 1588 functions...................................................................................................................................... 1943 55.6.11 FIFO thresholds..............................................................................................................................................1947 55.6.12 Loopback options...........................................................................................................................................1950 55.6.13 Legacy buffer descriptors...............................................................................................................................1951 55.6.14 Enhanced buffer descriptors...........................................................................................................................1952 55.6.15 Client FIFO application interface.................................................................................................................. 1958 55.6.16 FIFO protection..............................................................................................................................................1961 55.6.17 Reference clock..............................................................................................................................................1963 55.6.18 PHY management interface........................................................................................................................... 1964 55.6.19 Ethernet interfaces..........................................................................................................................................1967 Chapter 56 Debug 56.1 Introduction...................................................................................................................................................................1973 56.2 CM4 and CM0 ROM table......................................................................................................................................... 1976 56.3 Debug port.................................................................................................................................................................... 1977 56.3.1 JTAG-to-SWD change sequence................................................................................................................... 1978 56.4 Debug port pin descriptions..........................................................................................................................................1979 56.5 System TAP connection................................................................................................................................................1979 56.5.1 IR codes..........................................................................................................................................................1979 56.6 MDM-AP status and control registers.......................................................................................................................... 1980 56.6.1 MDM-AP Control Register............................................................................................................................1981 56.6.2 MDM-AP Status Register.............................................................................................................................. 1982 56.7 Debug resets..................................................................................................................................................................1983 56.8 AHB-AP........................................................................................................................................................................1984 56.9 ITM............................................................................................................................................................................... 1984 56.10 Core trace connectivity................................................................................................................................................. 1985 56.11 TPIU..............................................................................................................................................................................1985 56.12 DWT............................................................................................................................................................................. 1986 56.13 MTB .............................................................................................................................................................................1986 S32K1xx Series Reference Manual, Rev. 9, 09/2018 NXP Semiconductors 47 Section number Title Page 56.14 Debug in low-power modes..........................................................................................................................................1987 56.14.1 Debug module state in low-power modes......................................................................................................1987 56.15 Debug and security....................................................................................................................................................... 1988 Chapter 57 JTAG Controller (JTAGC) 57.1 Chip-specific JTAGC information................................................................................................................................1989 57.2 Introduction...................................................................................................................................................................1989 57.2.1 Block diagram................................................................................................................................................ 1989 57.2.2 Features.......................................................................................................................................................... 1990 57.2.3 Modes of operation........................................................................................................................................ 1990 57.3 External signal description............................................................................................................................................1992 57.3.1 Test clock input (TCK).................................................................................................................................. 1992 57.3.2 Test data input (TDI)......................................................................................................................................1992 57.3.3 Test data output (TDO).................................................................................................................................. 1992 57.3.4 Test mode select (TMS).................................................................................................................................1993 57.4 Register description...................................................................................................................................................... 1993 57.4.1 Instruction register......................................................................................................................................... 1993 57.4.2 Bypass register............................................................................................................................................... 1993 57.4.3 Device identification register......................................................................................................................... 1994 57.4.4 Boundary scan register...................................................................................................................................1994 57.5 Functional description...................................................................................................................................................1995 57.5.1 JTAGC reset configuration............................................................................................................................ 1995 57.5.2 IEEE 1149.1-2001 (JTAG) TAP....................................................................................................................1995 57.5.3 TAP controller state machine.........................................................................................................................1995 57.5.4 JTAGC block instructions..............................................................................................................................1998 57.5.5 Boundary scan................................................................................................................................................2001 57.6 Initialization/application information........................................................................................................................... 2001